Please use this identifier to cite or link to this item:
https://thuvienso.dau.edu.vn:88/handle/DHKTDN/6572| Title: | Verilog HDL a guide to digital design and synthesis |
| Authors: | Palnitkar, Samir |
| Keywords: | Digital Design Verilog HDL Synthesis |
| Issue Date: | 1996 |
| Publisher: | SunSoft Press |
| Abstract: | 1. Overview of Digital Design with Verilog HDL; 2. Hierarchical Modeling Concepts; 3. Basic Concepts; 4. Modules and Ports; 5. Gate-Level Modeling; 6. Dataflow Modeling; 7. Behavioral Modeling; 8. Tasks and Functions; 9. Useful Modeling Techniques; 10. Timing and Delays; 11. Switch-Level Modeling; 12. User-Defined Primitives; 13. Programming Language Interface; 14. Logic Synthesis with Verilog HDL; 15. Appendixes; 16. Index. |
| URI: | https://thuvienso.dau.edu.vn:88/handle/DHKTDN/6572 |
| Appears in Collections: | Ngoại Văn |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Verilog HDL a guide to digital design and synthesis.6051.pdf | 11.37 MB | Adobe PDF |  View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.