Verilog HDL a guide to digital design and synthesis

Please use this identifier to cite or link to this item: https://thuvienso.dau.edu.vn:88/handle/DHKTDN/6572

Full metadata record

DC Field	Value	Language
dc.contributor.author	Palnitkar, Samir	-
dc.date.accessioned	2014-12-29T03:45:40Z	-
dc.date.available	2014-12-29T03:45:40Z	-
dc.date.issued	1996	-
dc.identifier.uri	https://thuvienso.dau.edu.vn:88/handle/DHKTDN/6572	-
dc.description.abstract	1. Overview of Digital Design with Verilog HDL; 2. Hierarchical Modeling Concepts; 3. Basic Concepts; 4. Modules and Ports; 5. Gate-Level Modeling; 6. Dataflow Modeling; 7. Behavioral Modeling; 8. Tasks and Functions; 9. Useful Modeling Techniques; 10. Timing and Delays; 11. Switch-Level Modeling; 12. User-Defined Primitives; 13. Programming Language Interface; 14. Logic Synthesis with Verilog HDL; 15. Appendixes; 16. Index.	vi
dc.language.iso	en	vi
dc.publisher	SunSoft Press	vi
dc.subject	Digital Design	vi
dc.subject	Verilog HDL	vi
dc.subject	Synthesis	vi
dc.title	Verilog HDL a guide to digital design and synthesis	vi
dc.type	Book	vi
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